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JPS6417128A Expired / Lapsed JP ⏱️ 0.0 years remaining

Dynamic arrangement system for domain area of virtual computer

Assignee: Fujitsu Ltd
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Filing: 1987-07-10
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Granted: —
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Expires: 2007-07-10
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Abstract

Abstract PURPOSE:To realize the continuation of the processing of a virtual computer which so far used an area including a memory error, by rearranging the information stored said area including the memory area into an idle area of a relevant memory. CONSTITUTION:When an error occurs in an area 31 of a main memory working in an operating system OS1, the operations of a CPU and an input/output device 8 which are used by the OS1 are stopped by a control program CP. Then the contents of the OS1 stored in the area 31 are moved to an idle area 4. Furthermore the registers (ABR and ALR) holding the value to check the propriety of the address value of the main memory when an access is given to this memory and a register (AMR) holding the value to check the propriety of the address value when a channel gives an access to the main memory are converted into the address values of the area 4. Then the OS1 is restored to its normal operation.

Inventors

  • 👤 Yukiyoshi Omura

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-30 00:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4843

Claims Analysis

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References Cited (Backward Citations)

JPS5888900A Cited
JPS5990294A Cited
JPS61195444A Cited

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