Method for forming multilayered interconnection and semiconductor device using same

Abstract

Abstract PURPOSE:To make it possible to easily perform the planarization even the wiring is formed in a multilayer, by forming, in the insulating film of the ground layer of the wiring, a groove having a width wider than the wiring width and the same pattern, thereby reducing the step between the upper surface of the wiring and the upper surface of the ground layer insulating film. CONSTITUTION:After forming a semiconductor element 12 on a wafer 10, an insulating film 18 is thickly formed on the whole surface thereof by CVD. Then, after a negative resist 24 is applied on the insulating film 18, it is exposed to light through a glass mask 25 for the aluminum wiring of the first layer, and the unexposed part is etched off. Then, with the negative resist 24 as a mask the insulating film 18 is etched to form a groove 20. The width of the groove 20 is established by adjusting the over etching amount so that it has a gap which prevents an aluminium wiring 19 from projecting out from the groove 20 and allows an inter-layer insulating film 21 to be buried between the aluminium wiring 19 of the first layer and the groove 20. At this time, the upper surface of the insulating film 18 except for the groove 20 and the upper surface of the aluminium wiring of the first layer are in substantially the same position, and accordingly, the inter-layer insulating film 21 can flatly be formed.

Inventors

• 👤 Atsuo Omiya

Bibliographic Details