← Back to Patent Explorer
JPS6415948A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor integtated circuit

Assignee: NEC Corp
•
Filing: 1987-07-09
•
Granted: —
•
Expires: 2007-07-09
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To reduce the occurrence of a noise due to the effect between cells and to prevent the malfunction by providing, for each split cell region, a power supply wiring pattern and a ground wiring pattern which are respectively connected to independent power supply and ground pads, thereby eliminating the effect between cells. CONSTITUTION:To a first split cell region 1, a power supply and a ground voltage are supplied through a power wiring pattern 6 from a power supply pad 4 and a ground wiring pattern 7 from a ground pad 5. Also, to a second split cell region 2, a power supply and a ground voltage are supplied through a power wiring pattern 16 from a power supply pad 8 and a ground wiring pattern 17 from a ground pad 9. Further, the respective power supply pads 4, 8 and ground pads 5, 9 of an input/output terminal region 3 are separately connected to external power supply lines. Therefore, the two split cell regions 1 and 2 can obtain power supplies which are independent from each other, whereby the number of concurrent operations of the circuit can be increased.

Inventors

  • 👤 Takao Hirose

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 09:14
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag