Semiconductor integrated circuit device
Abstract
Abstract PURPOSE:To display the high speed performance of a chip in correspondence with the increase in number of input terminal and implementation of high density, by providing a lead wire, which is connected to the signal input terminal of an integrated circuit chip as a returning wire, which constitutes a feed through wire, and connecting a returning part and a bonding pad in a overlapped pattern. CONSTITUTION:A lead wire 4A forming an outgoing path is provided from an outer connecting terminal part 2 to the vicinity of a semiconductor circuit chip on a TAB board. A returning wire passes through the lead wire 4A and a lead wire 4B and returns to the external connecting terminal part. Thus a feed through wiring is formed with respect to the input terminal of a the chip. The lead wire 4 has a constant width d1. Ground conductors 2 and 3, which are set at a terminating potential VTT, are arranged with a constant interval d2 being provided. Thus, a coplanar transmission line is formed. The returning part has a concentric pattern, and the wire width d1 and the interval d2 are kept constant. Thus the coplanar transmission line having constant characteristic impedance is formed. A through hole is formed at the returning part, where the lead wire 4 draws an arc. Conductor layers 10 and 11 comprising Cu films, which are made of the same material for the lead wire 4, are connected to a bump electrode 9 of an input terminal pad 8 of the integrated circuit chip 7. The bump electrode 9 is formed by Au plating through a barrier metal layers of Ti-Ni-Pd and the like.
Inventors
- 👤 Tomoaki Takubo
- 👤 Kazuyoshi Saito
- 👤 Toshio Sudo
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.