Frame synchronizing clock generating circuit

Abstract

Abstract PURPOSE:To generate a clock synchronizing with a frame signal and having an optional frequency by providing a frequency division generating circuit detecting a value for high-level period and a value for low level period in an output clock. CONSTITUTION:Frequencies are represented as fb fb'=fc/X, where fF is a fre quency of a frame signal, fc is a basic clock synchronizing with it, fb is a clock required to generate, fb' is a generated approximate clock, M, N are the number of clocks fc, fb included in one frame, X is an integral number. In case of fb fb', since two values are obtained for the X, one is used for a value deciding the period where the output clock goes to a high level and the other is used as a value deciding the period where the clock is at a low level, and frequency division generating circuits X1, X2 detect them. Then the clock difference from fF and fb' is corrected by a phase adjustment counter 1 to synchronize the fF with the fb'.

Inventors

• 👤 Yoshiko Motoki
• 👤 Toshihiko Kurino

Bibliographic Details