Semiconductor device
Abstract
Abstract PURPOSE:To reduce the resistance of interconnections, by arranging interconnections having a double-layer structure, in which high melting point metal or silicide thereof is formed on polycrystalline silicon in a multilayer mode, and performing connection through a metal layer, which is provided on contact holes provided on the interconnection layers. CONSTITUTION:A first interconnection (a) is formed by laminating polysilicon 3 and a high melting point metal 4 on a field oxide film 2. The interconnection is covered with an interlayer film 8. A second interconnection (b) is formed by the similar way. A third interconnection (c) comprising aluminum 5 is formed on the interlayer film 8. Contact holes 7a and 7b are provided in the interlayer film 8 on the first and second interconnections (a) and (b). The high melting point metal 4 in each interconnection is exposed in the contact holes. A part of the aluminum 5 in the third interconnection (c) is arranged on the contact holes 7a and 7b. The high melting point metals 4 of the interconnections (a) and (b) are connected to each other. Therefore, high-resistance polycrystalline silicon is not present on the connecting path of a contact 7. The electric resistance in the first and second interconnection layers can be reduced.
Inventors
- 👤 Hitonori Hayano
- 👤 早野 仁紀
Bibliographic Details
Claims Analysis
Total Claims: 0References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.