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JPS6398142A Expired / Lapsed JP ⏱️ 0.0 years remaining

Pin grid array

Assignee: Panasonic Electric Works Co Ltd
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Filing: 1986-10-15
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Granted: —
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Expires: 2006-10-15
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Abstract

Abstract PURPOSE:To enhance the connecting reliability of pins to a circuit thereby to improve the conducting reliability between a semiconductor chip and the pins by forming part of the head of the pin of a conductive substance which can be remelted and solidified, and electrically connecting the pins to the circuit by the melted and solidified layer of the substance. CONSTITUTION:A plurality of pins 2 are buried fixedly to a substrate 1 to be projected from the substrate 1, a circuit 4 to be electrically connected to a semiconductor chip 3 to be mounted on the substrate 1 is provided on the substrate 1, and part of the head 2a of the pin 2 is formed of a conductive substance 5 which can be remelted and solidified. The head 2a is heated to melt the substance 5, which is filled in a fluidized state in the lower part of a recess 7 of a pin hole 24, and the pins 2 are electrically connected to the circuit 4 by a melted and solidified layer 6. Thus, the electric connection between the pins 2 and the circuit 4 is obtained by the layer 6 of the substance 5 to enhance the conductive reliability between the chip 3 and the pins 2.

Inventors

  • 👤 Atsumi Hirata
  • 👤 平田 篤臣
  • 👤 Yoshihiko Nakamura
  • 👤 善彦 中村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 22:48
CPC Classifications
—

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