Time division multiple access communication system

Abstract

Abstract PURPOSE:To improve the frame utilizing efficiency by recovering a clock synchronized with a master station by a clock recovery circuit and synchronizing the frequency switching with a frame timing clock from the master station so as to reduce a guard time. CONSTITUTION:A reception signal fed to a reception input terminal 11 is inputted to a descrambler 16 and a frame detection circuit 17 via a frequency converter 12 and a demodulator 15 and a reception data is outputted from the descrambler 16 and the frame signal is outputted from the circuit 17. Moreover, the output of the demodulator 15 is supplied also to the clock recovery circuit 22 to recover the clock synchronized with that of the master station. The clock is fed to a frequency switching control circuit 18, which counts the recovered clock based on the detection frame signal and the selection circuit 13 is controlled in the optimum timing during the guard time. Thus, the frequency is switched in synchronism with the frame timing and the clock from the master station, then the guard time is decreased and the frame utilizing efficiency is improved.

Inventors

• 👤 Kojiro Tajima
• 👤 田島　浩二郎
• 👤 Osamu Kurita
• 👤 修 栗田
• 👤 Tamaaki Yoshida
• 👤 彰顕 吉田

Bibliographic Details