Output circuit

Abstract

Abstract PURPOSE:To avert the danger of latchup in a MOS integrated circuit by adding two switching transistors (TRs) and a resistive element. CONSTITUTION:In order to obtain a differentiation signal CE2 of a control signal CE1, a differentiation pulse generating circuit is constituted by an Ex-OR gate G4 and a delay gate G5. The differentiation signal CE2 is fed to a gate of a P-channel MOS TR Q3 and the inverting signal being the inverse of the differentiation signal CE2 by an inverter G6 is fed to a gate of a P-channel MOS TR Q4. The signal CE1 goes to a high level in the time slot at which the output signal is to be given, and the source of the TR Q1 is connected to a power supply via a resistive element and the TR Q3 at the leading and trailing edges of the time slot to supply the output signal by the control of the differentiation signal CE2, and the source of the TR Q1 is connected directly to the power supply through a TR Q4 at the times other than the leading and trailing edges. Thus, in selecting the resistance of the resistive element 1 properly, no latchup is caused even with overlapped signals CE1.

Inventors

• 👤 Shoichi Saito
• 👤 齊藤　正一

Bibliographic Details