Field effect transistor

Abstract

Abstract PURPOSE:To contrive the reduction in a parasitic capacitance by a method wherein an electrode for lead-out is integrally formed on the surface of each region of source and drain regions and each electrode of source and drain electrodes, and at the same time, the overlap of an element forming region with each electrode of the source and drain electrodes is lessened. CONSTITUTION:An Si oxide film 4 is formed on the surface of an element forming region 2 and a gate electrode 5, a source electrode 6 and a drain electrode 7 are formed on this Si film 4. With an electrode 10A for source region lead-out provided on the side surface of the source electrode 6 and part of the surface of a source region 8, an electrode 10B for drain region lead-out is integrally formed on the side surface of the drain electrode 7 and part of the surface of a drain region 9. According to such a way, the lead-out to the electrodes can be executed without using a contact hole. Moreover, the overlap of the element forming region 2 with the source and drain electrodes 6 and 7 can be lessened. As a result, the parasitic capacitance between the element forming region 2 and a substrate 1 can be reduced because the areas of the source region 8 and the drain region 9 become smaller.

Inventors

• 👤 Isamu Miyagi
• 👤 宮城　勇

Bibliographic Details