Block access system for changeable access cycle

Abstract

Abstract PURPOSE:To increase the flexibility of a system by changing over an access cycle at the time of block access execution depending on the type of response signal returned from a bus slave. CONSTITUTION:The CPU of a bus master side reads necessary data from an external memory M of the bus slave side, when the necessary data are not found in a cache memory C. For this purpose, a control circuit A transmits a block access request signal BLOCK to the bus slave. A control circuit B to receive such a signal returns a response signal BLOCKF or BLOCKS respectively to the bus master side depending on an block access executed whether by a high speed transfer system or by a low speed transfer system. The control circuit A to receive this, transfers a data memory from the external memory M to a memory C by changing over an access cycle depending on the type of response signal. Thus, a different memory in an access time can be freely used and the flexibility of the system can be increased.

Inventors

• 👤 Masahito Mihashi
• 👤 雅人 三橋
• 👤 Takeshi Kitahara
• 👤 北原　毅

Bibliographic Details