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JPS6329541A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Hitachi Microcomputer System Ltd
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Filing: 1986-07-23
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Granted: —
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Expires: 2006-07-23
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Abstract

Abstract PURPOSE:To detect the position deviation of patterns quickly and readily, by aligning cells in a matrix form, and overlapping the cells on a semiconductor substrate so that cell aligning pitches are different. CONSTITUTION:Rectangular cells are aligned in a matrix form. The pitch of the grid of a grid shaped pattern 6 for forming a reference layer is different from the pitch of a cell shaped pattern 7 for forming an aligning layer. In a reducing aligner, the pattern is reduced and transferred on a secmiconductor substrate 1 through a lens 8. If the cells, which are located at the central positions of the reference layer 2 and the alignging layer 3, are perfectly overlapped, when the deviation is not found in the alignment of the masks, the position of the cells perfectly overlapped is formed at a point which is deviated from the center of the reference layer 2 in the X or Y direction when the deviation is present in the alignment of the masks. The direction and the magnitude of the devaition in alignment can be detected quickly and readily by finding the perfectly overlapped part of the cells in the reference layer 2 and the aligning layer 3.

Inventors

  • 👤 Katsuhiro Nozaki
  • 👤 野崎 勝弘
  • 👤 Fumiyoshi Sato
  • 👤 佐藤 文良
  • 👤 Maki Nagao
  • 👤 長尾 眞樹
  • 👤 Aritoshi Sugimoto
  • 👤 有俊 杉本
  • 👤 Kazuyuki Sumukai
  • 👤 一行 須向
  • 👤 Ichiro Uehara
  • 👤 一郎 上原

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-06 13:49
CPC Classifications
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