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JPS6325758A Expired / Lapsed JP ⏱️ 0.0 years remaining

Slave processor

Assignee: NEC Corp
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Filing: 1986-07-18
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Granted: —
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Expires: 2006-07-18
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Abstract

Abstract PURPOSE:To shorten a program loading time by providing a data buffer between an internal bus and a common bus, outputting an internal state onto a common bus via a status buffer and mapping the contents of a local memory over a common memory. CONSTITUTION:An internal bus 120 is connected to a common bus 121 via a data buffer 4 and an internal state is outputted onto a common bus 121 via a status buffer 5. A holding signal is produced so that a local CPU 1 is set by the reset signal of the bus 121 or a specific I/O instruction and then reset by another I/O instruction. Then the CPU 1 is held by said holding signal and the contents of a local memory 3 are mapped over a common memory 13.

Inventors

  • 👤 Toshihiko Sato
  • 👤 敏彦 佐藤

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-28 05:08
CPC Classifications
—

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