Vertical insulated-gate type field effect transistor

Abstract

Abstract PURPOSE:To reduce a space between wells without increasing the ON resistance of a vertical double-diffusion MOSFET (VDMOS) and decrease the product (Rons) of the area of an element and the ON resistance, by forming a groove in a semiconductor substrate between neighboring base body regions, and making the concentration of first conductivity type impurities around said groove in the semiconductor substrate higher than that in a drift region. CONSTITUTION:A groove 20 is formed in a region held between wells 13. The concentration of impurities around the groove is made high, and the resistance at this part is decreased. Namely, the impurities, whose concentration is higher than that in another drift region 11, is introduced in a contact part of the groove 20 and the drift region 11. Therefore, even if a depletion layer is expanded toward the drift region 11 from the boundary part between the wells and the drift region, a high concentration impurity layer 21 around the groove is not depleted, and a low resistance state can be kept. Thus the Rons of a VDMOS can be decreased without impairing the breakdown strength of an element and without requiring especially high machining accuracy.

Inventors

• 👤 Yoshiaki Yazawa
• 👤 義昭 矢澤
• 👤 Takahiro Nagano
• 👤 隆洋 長野

Bibliographic Details