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JPS63253706A Expired / Lapsed JP ⏱️ 0.0 years remaining

Differential circuit

Assignee: NEC Corp
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Filing: 1987-04-09
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Granted: —
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Expires: 2007-04-09
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Abstract

Abstract PURPOSE:To allow the output to follow the input at a high speed by providing a switch circuit whose on/off is controlled by a control signal between drains of two MOS transistors (TRs). CONSTITUTION:A reset PMOS transistor (TR) Ms is provided, whose drain- source path is connected between drains of MOS TRs M1, M2 of a differential pair and whose gate receives an on/off control voltage Vc. In bringing the control signal Vc to a ground level to turn on the reset PMOS TR M5, the drain potential of the two TRs M1, M2 is nearly equal to each other and the differential circuit 1 is brought forcibly into the unsaturated area. That is, just before an input signal is given to the differential circuit, or just after the input signal is given, the switch circuit is turned on, even when the differential circuit is in the saturated region, the momentary transition of the unsaturated region is attained, and the differential circuit tracing the input signal at a high speed is obtained.

Inventors

  • 👤 Toshiyuki Hotta
  • 👤 堀田 寿之
  • 👤 Shinji Masuda
  • 👤 増田 愼治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 21:07
CPC Classifications
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