Multiplying circuit

Abstract

Abstract PURPOSE:To generate a 2-multiple clock excellent in duty by selecting a delay clock extracted in response to the position of a delay clock phase-shifted by a phase of 1/2 period or over of an input clock in a phase detection delay circuit section. CONSTITUTION:A selector control signal corresponding to the extracted position of the phase detection delay clock having a phase exceeding the phase of the input clock CK detected at a phase detection section 6 at first by a 1/2 period of the clock in the extracted position of a phase detection delay circuit section 5 is outputted from the phase detection section 6 to a selector 7. Thus, A delay clock CKD3 is selected when the operating time of the inverter in, e.g., a delay circuit section 1 is faster in response to the selector control signal outputted from the phase detection section 6, then the delay clock CKD 3 is selected by the selector 7, and when the operation time of the inverter is slow, the delay clock CKD1 is selected. Thus, the clock CK2F having a double frequency is outputted to an output terminal 4 to generate a 2 multiple clock excellent in duty.

Inventors

• 👤 Masahisa Yoshimi
• 👤 吉見　昌久
• 👤 Norio Murakami
• 👤 典生 村上

Bibliographic Details