semiconductor storage device

Abstract

Abstract PURPOSE:To increase the number of memory cells to be simultaneously accessed and to shorten a test time by setting up only partial memory mats including memory cells to be selected at the time of a normal mode to a selected state, and setting up all the memory mats to the selected state at the time of a test mode. CONSTITUTION:The partial memory mats including a memory mat having at least memory cells to be selected out of plural memory mats M0-M3 is set up to the selected state and the residual memory mats are set up to the non-selected state in accordance with address specification at the time of normal memory access, and at the time of the test mode, address signals specifying the memory mats M0-M3 are practically invalidated, all the memory mats M0-M3 are set up to the selected state and their reading signals are supplied to a decision circuit TLG. Since the selecting operation of the memory mats M0-M3 is switched in accordance with the normal memory access and the test mode, power consumption can be reduced at the time of normal operation and the test time can be shortened in the test mode.

Inventors

• 👤 Yuji Sakai
• 👤 祐二 酒井

Bibliographic Details