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JPS632373A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: NTT Inc
•
Filing: 1986-06-23
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Granted: —
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Expires: 2006-06-23
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Abstract

Abstract PURPOSE:To prevent the lowering of the accuracy of finishing generated in a process after the formation of a groove having wide width to a contact section and the generation of a short circuit due to the defective alignment of a contact hole by shaping the groove to the contact section. CONSTITUTION:Both groove width are equalized in a memory section and a contact section. A high-concentration impurity doped layer 14 having a conductivity type opposite to that of a substrate is formed around the groove in the contact section, a contact hole 12 is shaped onto one part of said high- concentration impurity doped layer 14 and the groove 2, and a metallic wiring layer 13 is connected to the high-concentration impurity doped layer 14 and a cell plate buried into the groove 2 through the contact hole 12. The high- concentration impurity doped layer connected to a conductor layer buried into the groove and having the conductivity type reverse to the substrate is formed around the groove in the contact section, thus generating no short circuit due to the contact of the wiring layer and the semiconductor substrate as seen in conventional techniques even when the contact hole extends over regions except the groove.

Inventors

  • 👤 Kazushige Minegishi
  • 👤 峯岸 一茂
  • 👤 Takashi Morie
  • 👤 隆 森江
  • 👤 Ban Nakajima
  • 👤 中島 蕃

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 07:03
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37

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