Semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To limit an unused wiring channel region to the minimum degree and to prevent the increase in chip area, by arrangine MOS transistors and bipolar transistors on the entire surface in a chip on a specified repeating unit basis, and appropriately using the MOS transistors and the bipolar transistors as logic elements or wiring regions. CONSTITUTION:Many CMOS basic cell lines are juxtaposed in the direction at a right angle with a basic cell line. At least one or more lines of bipolar CMOS basic cell lines are included between the CMOS basic cell lines. Namely, bipolar transistors 32 and a configuration, in which a pair of a PMOS 33 and an NMOS 34 are held between the bipolar transistors 32, are made to be one basic cell unit. Said units are repeatedly arranged on the entire surface of a chip. The basic cells are sequentially used as wiring regions with the bipolar element and the MOS element as basic units. Thus the bipolar and MOS transistors neighboring wiring channel regions can be utilized without remaining parts, and one logic element can be formed.

Inventors

• 👤 Fumio Murabayashi
• 👤 文夫 村林
• 👤 Yoji Nishio
• 👤 洋二 西尾

Bibliographic Details