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JPS63166332A Expired / Lapsed JP ⏱️ 0.0 years remaining

Data receiver

Assignee: NEC Corp
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Filing: 1986-12-27
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Granted: —
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Expires: 2006-12-27
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Abstract

Abstract PURPOSE:To improve the transmission efficiency by varying a bus memory length of a Viterbi decoder depending on the quality of a transmission line so as to reduce the delay in the inside of the Viterbi decoder when the quality of the transmission line is excellent. CONSTITUTION:A measuring means using a Viterbi decoder 103 setting the internal path memory length variably as a Viterbi decoder and a selector 108 and measuring the degree of quality of the transmission line and outputting the result of measurement, a discriminator 102, a subtractor 104, a square device 105, an averaging device 106 and a controlling means 107 setting the path memory length of the Viterbi decoder short when the result of measurement represents the excellent quality of transmission line by the share are provided. When the quality of the transmission line is excellent, the internal delay in the Viterbi decoder is reduced and the transmission efficiency is improved.

Inventors

  • 👤 Atsushi Yoshida
  • 👤 厚 吉田

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-26 10:05
CPC Classifications
—

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