Semiconductor device and manufacture thereof

Abstract

Abstract PURPOSE:To make the capacity value highly precise by determining the number of the correction capacitors to be connected in parallel with the main capacitor by partial cutting after the formation of a metallic wiring or by the mask selection at the time of forming the metallic wiring. CONSTITUTION:In the surface of a P-type substrate 11, an N<+> buried layer 12, an N<-> epitaxial layer 13 and a field oxide film 15 are sequentially formed, and isolation and diffusion are performed to form an island. Then N<+> diffusion is deeply performed in this island to form an N<+> diffusion region 14, and on the surface thereof, the field oxide film is grown. Then the field oxide film 15 is patterned, forming a gate oxide film 16 in the N<+> diffusion region surface in the bottom surface of this opening part. Next, a contact patterning is applied to the field oxide film 15 and a metallic wiring patterning is performed to form an electrode A and a metallic wiring 1 integrally communicating therewith, and electrodes B, C1-C4 and a metallic wiring 2 integrally communicating therewith. Further, part of the electrodes C1-C4 for correction capacitors are cut so as to be disconnected from the metallic wiring 2 to obtain the metallic wiring 2. With this, a title device having high-precision MOS capacitors can be formed with a good yield.

Inventors

• 👤 Kazuo Kihara
• 👤 木原　和雄

Bibliographic Details