Logic circuit

Abstract

Abstract PURPOSE:To speed up the time pulling up/down an output terminal by providing a 3-state buffer and a MOS transistor (TR) whose drain is connected to the output terminal of the buffer, and is electrified only when the 3-state buffer is at a high impedance. CONSTITUTION:In using a P-channel MOS TR for pull-up, a drain of the P- channel MOS TR B is connected to an output terminal 3 of the 3-state buffer A, the gate connects to a control input signal 2, and the source is connected to a power supply VDD, respectively. When the control input signal 2 is at logical '0', the output of the buffer A is at a high impedance, but since the pull-up is operated due to the turning-on of the TR B and the level of the output terminal 3 goes to logical '1'. The processing in using an N-channel MOS TR D for pull-down operation. When the control input signal 2 at logical '1' in both the cases, since the TRs B, D are turned off, the equivalent resistance when the TRs B, D are turned on is lowered, pull-up/down at a fast speed is attained.

Inventors

• 👤 Kenichi Motohashi
• 👤 本橋　憲一

Bibliographic Details