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JPS6315435A Expired / Lapsed JP ⏱️ 0.0 years remaining

Package for semiconductor device

Assignee: Fujitsu Ltd
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Filing: 1986-07-08
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Granted: —
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Expires: 2006-07-08
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Abstract

Abstract PURPOSE:To reduce an occupying area required for packaging, and to increase electrostatic resistance by fitting elements, such as a resistor, a capacitor, etc., crossing a section between a pad added near a semiconductor-chip loading region and a lead wire and connecting a bonding wire to the pad. CONSTITUTION:Pads 6 for element loading loading elements, such as a resistor, a capacitor, etc. are added near a semiconductor-chip loading region 2, and the elements 7, such as the resistor, the capacitor, etc. are mounted, crossing sections among the pads 6 for loading the elements, such as the resistor, the capacitor, etc. and lead wires 3. Bonding wires 4 are set up among a semiconductor chip 5 and the pads 6 for element loading loading the elements, such as the resistor, the capacitor, etc. or the lead wires 3. When the elements 7, such as the resistor, the capacitor, etc. are unnecessitated, the bonding wires 4 are connected directly to the lead wires 3. Accordingly, an occupying area needed for packaging is reduced, and electrostatic resistance is increased.

Inventors

  • 👤 Hirokazu Tanaka
  • 👤 田中 裕計
  • 👤 Kenichi Nakamura
  • 👤 健一 中村

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 02:55
CPC Classifications
H; H10; H10W; H10W72/00; H10W72/50; H10W72/541; H10W72/5449

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