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JPS63150A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor memory

Assignee: Toshiba Corp
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Filing: 1986-06-19
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Granted: —
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Expires: 2006-06-19
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Abstract

Abstract PURPOSE:To reduce the area of a memory cell by forming a channel region in a transistor for transfer and a capacitor for memory to one side wall of an island region and shaping two memory cells in one island region. CONSTITUTION:Word lines 21 and bit lines 22 mutually crossed at right angles and formed to a latticed shape are formed, and a plurality of unit memories 101,102 ... are each shaped among pairs of the word lines 21. The respective unit memory cell is constituted of transistors for transfer formed on one side surfaces in grooves shaped to a semiconductor substrate and capacitors communicated with the transistors for transfer and formed on the same side surfaces in the same grooves. The semiconductor substrate such as a P-type one 23 is used, and a plurality of the grooves 24 are each shaped in parallel through reactive ion etching (RIE), etc. to the substrate 23. Accordingly, areas occupied by the memory cells are reduced, thus allowing the increase of density.

Inventors

  • 👤 Atsuhiko Menju
  • 👤 毛受 篤彦
  • 👤 Toshiharu Watanabe
  • 👤 渡辺 寿治

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-05 19:37
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/37

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