Semiconductor memory

Abstract

Abstract PURPOSE:To maintain the high speed properties of a large scale semiconductor memory even at the time of constituting the memory by organizing a bit line or a word line of a metallic wiring, changing the metallic wiring into multilayers and forming a metallic wiring as an upper layer onto a flat insulating film coating a metallic wiring as a lower layer. CONSTITUTION:Bit lines 9 and 12 as metallic wirings are shaped in multilayers, and the metallic wirings as upper layers such as the bit lines 12 in the figure are formed onto a flat insulating film 11. Consequently, even when the thickness L1 of the insulating film 11 is brought to 1mum and a distance L2 viewed in a plane manner between the bit line 9 and the bit line 12 is brought to 1mum, the shortest distance L3 between these bit lines is brought to 1.4mum, and the value of parasitic capacitance between these lines is made smaller than the bit line 9 and the bit line 12 are disposed on the same plane, keeping the distance of 1mum. Accordingly, even when a large scale semiconductor memory in which parasitice capacitance generated among the bit lines or the word lines can be reduced is constructed, high speed properties thereof can be maintained.

Inventors

• 👤 Shuichi Harajiri
• 👤 原尻　秀一

Bibliographic Details