Emphasis circuit

Abstract

Abstract PURPOSE:To decrease the amount of emphasis in a stage of pneemphasis at a time when a large amplitude signal is inputted by providing a circuit to multipy an amplitude-limited signal with a second coefficient and to subtract the product from an input video signal. CONSTITUTION:An input signal a1 is supplied to a high-pass filter 9 via a substractor 7 and is used as a signal c1, then amplitude-limited in a limiter 3 to come to be a signal d1. The signal d1 is multiplied by the coefficient K(smaller than one) in a coefficient circuit 8, supplied to the subtractor 7 where it is subtracted from the input signal a1, and goes to a signal b1. The signal d1 is multiplied by X(larger than one) in a coefficient circuit 4, then is added to the input signal a1 in an adder 5 and is used as a signal e1. Which is taken out from an output terminal 6. Since a loop made of the limiter 3 and the coefficient circuit 8 is thus provided, the transfer fuction GL of the limiter 3 gradually approaches zero at a time when a large-amplitude signal is inputted, and its response becomes quicker. As a result, at the said time of large- amplitude signal inputting, the amount of emphasis of the system becomes smaller.

Inventors

• 👤 Yasutoshi Matsuo
• 👤 泰俊 松尾
• 👤 Makoto Nakano
• 👤 良 中野
• 👤 Mitsuo Harumatsu
• 👤 光男 春松
• 👤 Kojiro Muto
• 👤 武藤　孝次郎

Bibliographic Details