Junction field-effect transistor

Abstract

Abstract PURPOSE:To suppress the gate current in operation small in the case of a normally-off type J-FET by providing a barrier layer having a band gap larger than that of the channel region between the channel region and the gate region. CONSTITUTION:On a semi-insulating GaAs substrate 21, an n-GaAs layer becoming a channel region 22, an N-lGaAs layer becoming a barrier layer 23, and a n<+>-GaAs layer 24 becoming high-density source region 25 and drain region 26 are sequentially formed by a MOCVD method. Then, a recessed part 28 is formed, and the source region 25 and the drain region 26 are formed. Next, a gate region 29 of p<+>-GaAs in the recessed part 28, a source electrode 30S, a drain electrode 30D and a gate electrode 30G are formed. Subsequently, an inter-element isolation region 31 is formed, constituting a J-FET 32.

Inventors

• 👤 Hiroharu Kawai
• 👤 弘治 河合

Bibliographic Details