Decoding circuit

Abstract

Abstract PURPOSE:To realize a high speed action by boosting up the gate level of an FET with the aid of the pulsing signal of a decoder selected with row address information. CONSTITUTION:When word lines WL1-WL4 are selected by the input of address information, a decoder resetting signal phiP and the address signals AX1-AX3 of the selected decoder to to 'H', and N-MOSFETs QN11-QN13 are turned off. The joint N13 of the selected decoder becomes the pulsing signal at level 'L', a joint N14 through an inverter consisting of QP13 and QN14 turns 'L' to 'H'. A joint N3 also turns 'L' to 'H' level which is lower by threshold voltage of a QN3. The level of the joint N3 rises and information showing that the joint N14 is 'H' is transmitted to a joint N2 with totalling the delay time of the joint N14, N1 and N2 and that of two inverters. Thus the joint N3 is boosted up to level H twice as much as the former 'H'.

Inventors

• 👤 Yuji Nakaoka
• 👤 裕司 中岡

Bibliographic Details