Optimization processor for large-scaled combination problem

Abstract

Abstract PURPOSE:To substantially reduce a processing time by executing in parallel the optimizing processing of combination elements with the aid of plural unit processors by employing a simulated annealing method. CONSTITUTION:Data on combination elements allocated by an allocating device 4 is stored in a storage device 13 in each unit processor. Upon the completion of the allocation to all the unit processors, a CPU 11 in the unit processor compares and operates according to the data on the combination elements read out of the storage device 13, and determines a state (branch) to be a next candidate. The compared and operated results are reported to a host computer 1 through a communicating equipment 12. When receiving the results from the unit processor, the host computer 1 reactivates the allocating device 4, and reallocates the combination elements data to the unit processors. While the device 4 is operating, the host computer 1 actually modifies the data on the combination elements, and stores the results in a storage device 3. Such a sequence is repeatedly performed, whereby optimum combinations can be sequentially determined from a tree combination.

Inventors

• 👤 Kaoru Kawamura
• 👤 薫 河村
• 👤 Hiroshi Shiraishi
• 👤 白石　博
• 👤 Toshiyuki Shibuya
• 👤 利行 澁谷
• 👤 Hideki Mito
• 👤 三渡　秀樹

Bibliographic Details