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JPS63115367A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Panasonic Holdings Corp
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Filing: 1986-11-04
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Granted: —
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Expires: 2006-11-04
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Abstract

Abstract PURPOSE:To enable a plurality of MOS type devices having different characteristics to be formed within a single groove by excavating grooves in a semiconductor substrate in two steps, and forming an impurity diffusion layer of the conductivity type opposite to the substrate in a limited side wall part of the groove formed in the latter step at an arbitrary depth from the substrate surface. CONSTITUTION:With three layer films 12-14 and a silicon nitride film 15 formed in the side wall as a mask, the silicon substrate part exposed in the bottom of a first groove 2 is anisotropically etched to newly form a second groove 2'. Then phosphorus is diffused to form an N-type impurity diffusion layer 3 in the side and bottom surfaces of the newly formed second groove 2'. The bottom of this groove 2' is further excavated by means of an anisotropic etching to form a third groove 2''. Subsequently boron ions are implanted into the bottom surface part of the third groove 2'' by the ion implantation method. In the trench type capacity, a P-type impurity diffusion layer 4 formed in the groove bottom acts as a device isolating region, and the P-type silicon substrate is exposed in the side surface of the upper groove part, in which part a device having different characteristics from the MOS capacity, for instance, a MOSFET of the enhancement type is formed.

Inventors

  • 👤 Nobuyuki Takenaka
  • 👤 竹中 信之

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 21:55
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038

Claims Analysis

Total Claims: 0
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References Cited (Backward Citations)

JPS5956763A Cited
JPS6123360A Cited
JPS61124167A Cited
JPS61239658A Cited
JPS62266868A Cited

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