Multi-CPU system bus

Abstract

Abstract PURPOSE:To perform transmission/reception of data between multi-CPU systems for each byte or block with no collision of data, by using a means which performs the general communication to all slave CPU systems and carries out transmission/reception of data with the slave CPU system having the transmission/reception right. CONSTITUTION:A master CPU system 11 sets a designated address of an interface part 12 to an address bus and therefore one or all interface parts 12 are activated. When data are transmitted to the slave CPU systems 13 from the system 11, the part 12 fetches data by a writing action carried out at the side of the system 11 and informs the existence of data to the system 13. Then the fetched data are delivered by a data reading action at the side of the system 13. The write and read inhibiting signals are controlled for each byte or block and the transmission of data is possible every plural bytes. Furthermore a series of data can be transmitted to the system 11 from the system 13 by repeating the above-mentioned operations.

Inventors

• 👤 Masahide Morozumi
• 👤 両角　昌英

Bibliographic Details