Digital-to-analog converter

Abstract

Abstract PURPOSE:To reduce number of gates by adopting the constitution that an active level period of an output signal per reference period is changed corresponding to a numeral of an input digital code so as to use a decoding gate in common. CONSTITUTION:Signals from counter 1-7, 33, 34 to frequency-divide a clock pulse CLK are decoded and output signals DE0''-DE5'' of each decoding gate generating an output in a period subject to bit weighting the used in common between channels having a different D-A conversion period (frequency), then a deficient decoding output is added between plural channels with different conversion frequencies and an excess decoding output is inhibited. Thus, number of gates isless and the power consumption is reduced.

Inventors

• 👤 Norihide Kinugasa
• 👤 教英 衣笠

Bibliographic Details