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JPS6288362A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacturing method of semiconductor device

Assignee: NEC Corp
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Filing: 1985-10-15
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Granted: —
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Expires: 2005-10-15
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Abstract

Abstract PURPOSE:To decrease parasitic base resistance accurately and to implement a high-speed bipolar transistor, by forming a graft base region by a self- alignment method with respect to an emitter region. CONSTITUTION:By utilizing the difference in impurity concentration in polysilicon, a non-doped polysilicon film 114 is selectively removed with KOH and the like, and a P<+> polysilicon film 115 is made to remain. Then, a silicon oxide film 112 is immersed in buffered flouric acid and removed. Thereafter, the device is immersed in a phosphoric acid solution, and the entire surface of a silicon nitride film 111 is removed. With the P<+> polysilicon film 115 as a mask, a silicon nitride film 107 is selectively removed. An opening part 116 is formed. A silicon nitride pattern 106A is also formed. The graft base region 116 is determined by the thickness of the silicon oxide film 112. Therefore, the device can be formed accurately and minutely, and junction capacitance is made small. The graft base region 116 is formed by a self-alignement method with respect to an emitter region 122. Therefore, it is not necessary to consider allowance margin, and the transistor size can be reduced.

Inventors

  • 👤 Yasuo Kadota
  • 👤 門田 靖夫

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-04 10:27
CPC Classifications
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