← Back to Patent Explorer
JPS6286870A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Panasonic Holdings Corp
•
Filing: 1985-10-14
•
Granted: —
•
Expires: 2005-10-14
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract PURPOSE:To accurately form an FET of offset gate structure by removing an insulating film of drain side on a gate electrode, then ion implanting, then with the film as a mask removing a gate electrode of the drain side. CONSTITUTION:After an N-type semiconductor layer 2 is formed on a GaAs substrate 1, a high melting point metal film 3 of the length corresponding to a distance between high melting point metal drain and source regions and an SiO2 film 4 are formed. Then, photoresist 5 as a mask the film 4 is partly removed, a silicon implanted layer 7 is formed. Then, with an SiO2 film 4' as a mask high melting point metal 3 is etched as a gate electrode 3'. The layer 7 is formed in a high density n-type semiconductor layer 8 by heat treating in arsenic atmosphere. Eventually, after a source electrode (not shown) is formed, the SiO2 film 4' is removed. Thus, an FET of offset gate structure can be accurately obtained.

Inventors

  • 👤 Takeshi Konuma
  • 👤 小沼 毅
  • 👤 Katsunori Nishii
  • 👤 勝則 西井

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-02 15:24
CPC Classifications
—

Claims Analysis

Total Claims: 0
No claims parsed yet. Click Sync Now above to re-index claims from Google Patents.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag