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JPS6286866A Expired / Lapsed JP ⏱️ 0.0 years remaining

Nonvolatile semiconductor memory

Assignee: Denso Corp
•
Filing: 1985-10-14
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Granted: —
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Expires: 2005-10-14
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Abstract

Abstract PURPOSE:To increase the integration by arranging a drain, an operating area, a floating gate, a control gate and a source for forming a memory cell in the thicknesswise direction of a semiconductor substrate. CONSTITUTION:An N<+> type impurity buried layer 20, an N<-> type epitaxial layer 30, and an oxide layer 40 are formed in a predetermined range on a P-type silicon substrate 10 having the same potential as a common ground terminal T1. Grooves are formed perpendicularly to the layer 20 from the surface of the layer 30 to form operating regions 31, 32,.... Insulator partitions are formed in the grooves, and floating gates 61, 62, control gates 71, 72 are disposed longitudinally therein. Impurity regions 81, 82 to become longitudinally therein. Impurity regions 81, 82 to become source and drain are formed together with the layer 20 on the regions 31, 32,.... Thus, the integration of the memory cell can be improved.

Inventors

  • 👤 Tetsuo Fujii
  • 👤 哲夫 藤井
  • 👤 Toshio Sakakibara
  • 👤 利夫 榊原
  • 👤 Nobuyoshi Sakakibara
  • 👤 伸義 榊原

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:21
CPC Classifications
H; H10; H10B; H10B69/00

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