Semiconductor memory device

Abstract

Abstract PURPOSE:To shorten the test time of a memory cell by dividing a memory cell matrix into plural parts, setting a switch means in a parallel processing mode when a switch control signal is at a specific state and returning said means in a normal action mode when the switch control signal is in states other than said specific one. CONSTITUTION:When the switch control signals is made at H, a switch 2 connects lines l1 and l2. Column address decoders 7 and 8 cocurrently act and select a specific memory cell in memory cell matrixes M1 and M2 with the aid of row address signals X1-X3 and column address signals Y1-Y3. Simultaneously a switch 3 acts to connect the bit line of the matrix M2 to the terminal 30b of a sense amplifier 30, and a parallel processing mode is set. Thus a variable range where the address selecting a memory cell changes halves, compared with a conventional method, whereby the test time of a memory cell can be shortened.

Inventors

• 👤 Toru Ichimura
• 👤 徹 市村

Bibliographic Details