Capacitor memory circuit

Abstract

Abstract PURPOSE:To enable using a capacitor with a large parasitic capacity as the capacitor for a memory without reducing the action speed by separating electrically other capacitor for the memory from a reading amplifier at the time of the writing and reading action of the signal. CONSTITUTION:Between respective capacitors 4-1-4-n for the memory and the negative polarity input terminal of a reading amplifier 2, the switch is added, only the capacitor for the memory during the reading action is connected to the negative polarity input terminal of the reading amplifier 2 and other capacitor for the memory is electrically separated. Thus, the parasitic capacity found at the negative polarity input terminal can be widely decreased and the action speed can be improved.

Inventors

• 👤 Kazuo Kondo
• 👤 和夫 近藤
• 👤 Shuzo Matsumoto
• 👤 脩三 松本
• 👤 Hisanobu Tsukasaki
• 👤 塚崎　久暢
• 👤 Mitsuo Nakajima
• 👤 満雄 中嶋
• 👤 Naomi Yoshida
• 👤 吉田　直実

Bibliographic Details