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JPS6281745A Expired / Lapsed JP ⏱️ 0.0 years remaining

Wafer-scale LSI semiconductor device and its manufacturing method

Assignee: Fujitsu Ltd
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Filing: 1985-10-05
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Granted: —
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Expires: 2005-10-05
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Abstract

Abstract PURPOSE:To improve a yield rate and to reduce costs, by arraigning a plurality of IC chips on a substrate, burying gaps between the chips on the substrate with a material, which has about the same expansion coefficient as that of the chips to the approximately same height as the upper surface of the chips, and forming a wiring layer, which connects the IC chips, on the substrate. CONSTITUTION:Silicon is buried in gaps between IC chips 2. A polysilicon or amorphous silicon layer 6 is grown on the entire surface of the wafer 4 by several mum. Then, the surface of the polysilicon layer 6 is flattened by a polishing process. Thus, an Si3N4 film 3 is exposed. After the Si3N4 film 3 is etched away once, an insulating film 7 is grown on the entire surface. Then, by using a photolithography method, holes are provided in pad parts 8, which are provided by the initial wafer process on the IC chips. An Al wiring layer 9 is evaporated on the entire surface. The wiring, which connects the IC chips is patterned. A protecting film 11 is further laminated, and the internal wiring is finished.

Inventors

  • 👤 Toshitaka Fukushima
  • 👤 福島 敏高

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-03 11:17
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/099; H10W70/60; H10W70/611; H10W72/00; H10W72/01; H10W72/0198; H10W72/30; H10W90/00; H10W70/67; H10W70/68; H10W70/682; H10W72/071; H10W72/073; H10W72/07331; H10W72/07337; H10W72/50; H10W72/551; H10W72/552; H10W72/5524; H10W72/59; H10W72/851; H10W72/874; H10W72/90; H10W72/941; H10W72/9413; H10W74/00; H10W74/01; H10W74/019; H10W90/10; H10W99/00

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