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JPS6269656A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Hitachi Microcomputer System Ltd
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Filing: 1985-09-24
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Granted: —
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Expires: 2005-09-24
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Abstract

Abstract PURPOSE:To reduce the parasitic capacity of a bonding pad by a method wherein a lower region whereon the bonding pad is formed is separated electrically from other regions by isolation. CONSTITUTION:In IC 21, a pad 23 is provided on the top of an oxide film 22. An Au wire 24 is connected to an inner lead. An N<-> epitaxial layer 25 under the pad 23 is surrounded by a P<+> isolation 26 at an earthing potential, forming an insular region of small area separated from other regions. An N<+> buried layer is not formed in this insular region, and the region is put in the state of floating. Although C11-C14 parasitic capacities are formed, the values of the capacities are very small, since these values are not reversely-biased.

Inventors

  • 👤 Tomoyoshi Kurisaki
  • 👤 栗崎 智義
  • 👤 Shigeru Kadokawa
  • 👤 滋 門川

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 01:27
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/50; H10W72/531; H10W72/536; H10W72/541; H10W72/5445; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/90; H10W72/921; H10W72/923; H10W72/931; H10W72/932; H10W72/934

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