Semiconductor device

Abstract

Abstract PURPOSE:To improve the reach through withstand voltage with an N<+> type buried layer of a high withstand voltage element and to simultaneously prevent the latchup of a CMOS by forming the position of an N-type buried layer directly under the CMOS near the main surface of semiconductor from the position of the N<+> type buried layer. CONSTITUTION:N<+> type buried layers 2A, 2B are formed on a P-type substrate formed with a recess on a region formed with a high withstand voltage element, element separating P<+> type diffused layers 4A-4C and N<+> type diffused layers 5A, 5B for reducing drain resistance are formed. N-well 6, P-well 7 for CMOS, polysilicon gates 9A-9C formed on a gate oxide film of approx. 1,000Angstrom , channel diffused layer 11 of DSA type high withstand MOSFET, P<+> type diffused layer 12A to become source and drain of low withstand voltage P-channel MOSFET, and an N<+> type diffused layer 13A to become source and drain of low withstand voltage N-channel MOSFET are formed, and contacting aluminum electrodes are formed to form an element. In this structure, the layer 3B of the element and the layer 3E of the CMOS can be independently formed in thicknesses.

Inventors

• 👤 Mitsuzo Sakamoto
• 👤 光造 坂本
• 👤 Takeaki Okabe
• 👤 岡部　健明
• 👤 Masatoshi Kimura
• 👤 正利 木村
• 👤 Koichiro Satonaka
• 👤 里中　孝一郎
• 👤 Takanori Nishimura
• 👤 西村　孝典
• 👤 Isao Sakamoto
• 👤 功 坂本

Bibliographic Details