Multiplexing system

Abstract

Abstract PURPOSE:To apply 24-channel multiplexing to a 2,400b/s data signal by adopting 24-frame form based on 133.3Hz for the multiplexing frame constitution of a digital data signal to a 64kb/s signal string. CONSTITUTION:The speed of a channel pulse is 20/18 times of the speed of a clock pulse and the signal is converted into a signal having a prescribed bearer speed by writing and reading a memory 12. An OR circuit 24 adds a frame synchronizing signal generated from a frame synchronizing signal generating circuit 23 to a data signal and a state signal corresponding to each channel to form a 64kb/s signal string, which is sent to the next terminal equipment. Further, a clock pulse generating circuit 14, a channel pulse generating circuit 16 and a frame synchronizing signal generating circuit (FGEN) 23 generate each pulse based on a reference pulse generated from a counter 21 in a data common section 20.

Inventors

• 👤 Masayuki Ohama
• 👤 大濱　雅幸
• 👤 Hideyuki Nakai
• 👤 中井　秀行
• 👤 Kuniharu Hirose
• 👤 広瀬　邦治

Bibliographic Details