Data separating circuit

Abstract

Abstract PURPOSE:To obtain compact, stable separate data regardless of variation in input level by applying the voltage generated by integrating a clock regenerated from the output of a comparator and holding its peak, and resetting the peak holding with a framing code detection output. CONSTITUTION:The regenerated clock 106 is integrated by an integration circuit 2. The DC voltage 103 of a peak holding circuit 3 is amplified by an amplifier 4 and supplied as a reference voltage 104 to an input of the comparator 5. A shift register 9 obtains parallel data 109 for framing code detection from the output 105 of the comparator 5 with the regenerated clock 106b of a clock regenerating circuit 6 and the next framing code decoder 8 decodes the parallel data 109 into a framing code. Then, the peak holding circuit 3 is reset with a constant time constant according to the detection result.

Inventors

• 👤 Toshihiko Tsuru
• 👤 鶴　俊彦

Bibliographic Details