Logical circuit

Abstract

Abstract PURPOSE:To increase operation speed by providing a bypass circuit for outputting directly an initial carry input signal as a carry output signal of the final stage, and also outputting an inversion logical signal of a carry signal, as an addition result output signal of each full adder. CONSTITUTION:When input signals A, B are inputted to each full adder 1, exclusive OR of A and B is outputted from an exclusive OR output terminal is outputted, and inputted to a NAND gate 8. In such a case, when (A0, B0)-(An, Bn) are all (1, 0) or (0, 1) the NAND gate 8 outputs '0', transmission gates 9-12 are close, and also transmission gates 13-16 are opened. That is to say, an operation result Sx and a carry output signal Cn of the final stage are outputted directly.

Inventors

• 👤 Satoshi Akiyama
• 👤 秋山　敏
• 👤 Yuichi Saito
• 👤 祐一 斉藤

Bibliographic Details