Manufacture of semiconductor integrated circuit device

Abstract

Abstract PURPOSE:To reduce the area of an isolation region and to contrive to enhance the integration of the titled device by providing processes for forming respectively a buried semiconductor region and a semiconductor region for isolation; which have the same conductivity type as those of the respective substrates between semiconductor element forming regions or the other conductivity type and also, have an impurity concentration higher than those of the substrates; on the major surface parts of the substrates. CONSTITUTION:The bottom part of the n-type well region of a p-channel MISFET Qp is constituted of a high-concentration buried semiconductor region 3B, the bottom part of the n-type well region of an n-channel MISFET Qn is constituted of a high-concentration buried semiconductor region 5A like the p-type well region and an isolation region is provided between the regions in which are formed the MISFET Qp and the MISFET Qn respectively that prevent latch-up respectively. Following the process for forming this insulating film 4 for interelement isolation, a p-type impurity is introduced in the major surface parts of the respective epitaxial layers 2 of the MISFET Qn forming region and the isolation region forming region and the buried semiconductor region 5A and a semiconductor region 5B for isolation are each formed.

Inventors

• 👤 Takahide Ikeda
• 👤 池田　隆英

Bibliographic Details