Memory circuit

Abstract

Abstract PURPOSE:To speedup the reading of data by rapidly making the voltage between data bus lines equal to each other by utilizing a first address clock and a second address clock generated in synchronization with and immediately after the ending of the first address clock. CONSTITUTION:A second address-clock circuit 12 generates the second address clock CP2 and its inverse clock in synchronization with the ending of the first address clock CP1. By said clocks, N-channel MOS transistors QB21 and QB22 and a P-channel MOS transistor QB18 are turned on, and the data bus lines 8 and 9 are shortcircuited, and rapidly lower to the low level of voltage. And the lines 8 and 9 become of the same voltage level when the second address clock ends.

Inventors

• 👤 Atsushi Oritani
• 👤 折谷　敦志

Bibliographic Details