Logic simulation

Abstract

Abstract PURPOSE:To detect a set-up timing error by generating a set-up timing error signal when the clock input has a change and a gate circuit is connected to a time wheel. CONSTITUTION:An automatic converting device 1 contains a gate to an FF. The data input and the clock input of the FF are defined as A and B respectively. The delay time of the input A is equal to the set-up time and the delay time of the input B is equal to zero. A control part 4 connects each element to a time wheel 2, when the element has an output change. A set-up timing error detector 3 receives the information showing whether the clock input has a change or not from the part 4 in case any gate circuit is connected to the wheel 2. When the clock input has a change, the detector 3 informs a set-up timing error to the part 4. In such a way, the set-up timing can be inspected.

Inventors

• 👤 Kenji Omori
• 👤 健児 大森

Bibliographic Details