Bus parity check circuit

Abstract

Abstract PURPOSE:To attain the mixed use of a circuit having a check circuit for bus parity and a circuit having no check circuit on a bus, by judging the propriety for execution of parity according to the presence or absence of a parity check enable signal. CONSTITUTION:When a read access is given to a parity presence slave 3 via a parity presence master 1, the lave 3 knows by an address signal on an address bus 5 that the slave 3 itself is selected. Thus the slave 3 delivers data to a data bus 6 and a data parity to a parity line 10 respectively. In this case, a signal PCENL is also delivered from a PCENL line 51 via a PCENL producing circuit 52a. The master 1 performs a parity check by the data and parity, and a parity generator checker 14a checks whether the data is normal or not. The checker 14a latches an abnormal signal if delivered. Then, whether the detection of faults is needed or not is judged by the signal PCENL.

Inventors

• 👤 Toshimichi Seki
• 👤 関　俊道

Bibliographic Details