Gate array master slice integrated circuit device

Abstract

Abstract PURPOSE:To increase the speed of signal transmission by reducing the longitudinal length of a unit cell when the same unit cells are constituted as well as to improve the degree of integration by making a wiring channel small by a method wherein the fundamental cell array of the titled device is composed of two columns of fundamental cells. CONSTITUTION:A wiring channel CH is provided outside a two-column fundamental cell array BC2, a wiring channel is not provided between one-column cell arrays BC1 and BC1' located in the array BC2, and the arrays BC1 and CB1' are arranged symmetrically. According to this arrangement, the longitudinal length of the fundamental cell can be made small, and as the wiring length can be reduced, signal characteristics can be improved, and moreover, a wiring channel region can also be reduced by the reduction of the number and length of wiring, thereby enabling to improve the degree of integration.

Inventors

• 👤 Shigeru Fujii
• 👤 藤井　滋
• 👤 Yoshihisa Takayama
• 👤 高山　良久

Bibliographic Details