Junction gate type field-effect transistor

Abstract

Abstract PURPOSE:To obtain a junction gate type field-effect transistor having self- alignment type gate structure, which has small parasitic resistance and noises therefrom are low, by forming a semiconductor buffer layer having a mixed- crystal composition different from a semiconductor gate layer between the semiconductor gate layer and a gate electrode metallic layer and shaping the gate electrode metallic layer to an eave form to the semiconductor buffer layer. CONSTITUTION:A first metal 5 and a second metal 6 for a gate electrode are patterned to a striped shape in the inverted mesa direction, and only a p type In0.74Ga0.26As0.56P0.44 layer 4 is etched selectively by an etching liquid consisting of sulfuric acid, hydrogen peroxide and water while using the metals 5 and 6 as masks. Only a p type InP layer 3 is etched selectively by an etching liquid composed of phosphoric acid and hydrochloric acid while employing the p type In0.74Ga0.26As0.56P0.44 layer 4 as a mask. The p type InP layer 3 is etched selectively without side etching and takes a form close to approximately verticality at that time. When a third metal 7 is evaporated onto the whole surface, the eave of the gate electrode shaped by selectively etching the p type In0.74Ga0.26 As0.56P0.44 layer 4 forms a shadow, thus isolating both a gate and a source and both the gate and a drain in a self-alignment manner.

Inventors

• 👤 Yasumasa Imoto
• 👤 井元　康雅

Bibliographic Details