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JPS6178162A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: Toshiba Corp
•
Filing: 1984-09-25
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Granted: —
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Expires: 2004-09-25
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Abstract

Abstract PURPOSE:To relax the concentration of an electric field in the curvature section of a main junction, and to increase withstanding voltage by forming a high-concentration impurity region having the same conduction type as a semiconductor substrate in a region on the back side of the semiconductor substrate so that the high-concentration impurity region is projected to a first impurity region and the width of the projection satisfies a specific condition. CONSTITUTION:A P conduction type base region 2 as a first impurity region is shaped on the main surface side of a semiconductor substrate 1, an emitter region 3 as a second impurity region is formed into the base region 2, and a guard ring region 4 is shaped on the main surface side of the semiconductor substrate 1. An N type high-concentration impurity region 5 is formed on the back side of the semiconductor substrate 1, and the side surface sections of the region 5 are set so as to be positioned between the emitter region 3 and the guard ring region 4. The position of the central section of the high-concentration impurity region 5 is made the same as that of the base region 2, and the region 5 is shaped so that the projection width T satisfies t T<=t+2WD. Where t represents the width of the first impurity region, T the projecting width of the high-concentration impurity region and WDS a space between the first impurity region and the high-concentration impurity region.

Inventors

  • 👤 Takeo Shiomi
  • 👤 塩見 武夫
  • 👤 Takao Emoto
  • 👤 江本 孝朗

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-09 03:19
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/102; H10D62/103; H10D62/105; H10D62/106; H10D64/00; H10D64/111; H10D64/115; H10D8/00

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